With the following progress and requirement in modern society, future electronic products must meet the standard aimed for high-speed process, multi-function, high-integration, thin, small, and lower cost. Therefore, the development of package technology is moving toward a trend of microminiaturization and high density. The frequent-used package technology comprises Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip (F/C), Multi-Chip Module (MCM) and so on.
With reference to FIG. 1, a conventional flip-chip package technology allocates a plurality of bond pads 11 onto an active surface 12 of a chip 10 in the arrangement of area array, thereafter forms a plurality of bumps 20 on each of the bond pads 11 and flips the chip 10. Next, the bumps 20 are electrically and mechanically connected with a plurality of mounting pads 31 of a substrate 30 (such as glass substrate, ceramic substrate or printed circuit board). Referring to FIGS. 2 and 3, in the process of conventional flip-chip package, an anisotropic conductive paste 40 can be disposed on the substrate 30. The bumps 20 may contact and extrude the anisotropic conductive paste 40 to force mentioned conductive paste 40 to flow from the bottom to the outside of the bumps 20. As a result, the extruded anisotropic conductive paste 40 is filled between the chip 10, the substrate 30 and adjacent bumps 20. However, the anisotropic conductive paste 40 is composed of a colloid 41 and a plurality of conductive particles 42. When the extruded anisotropic conductive paste 40 flows from the bottom to the outside of the bumps 20, those conductive particles 42 may gather between adjacent bumps 20 to lead a short phenomenon between the conductive particles 42 and adjacent bumps 20. Accordingly, the yield rate of the package process will be significantly influenced.